This invention relates to mask-programmable integrated circuit devices, and more particularly to making it possible to modify the performance of such devices after fabrication in a way that is programmable but that does not require mask modification.
An example of a mask-programmable device is a so-called structured ASIC (application-specific integrated circuit). See, for example, Chua et al. U.S. published patent application 2006/0001444A1. Such devices may be used to provide lower-cost alternatives to programmable logic devices (PLDs) or field-programmable gate arrays (FPGAs) that have been programmed in a particular way. (FPGA is used herein as a generic term, which also includes PLDs.) For example, after a user's logic design has been proven in a programmed FPGA implementation of that design, the design may be “migrated” to a structured ASIC implementation of the design. The structured ASIC may have certain masks that are the same or substantially the same for all structured ASIC products of that general kind. Only certain other masks need to be “customized” to implement a particular user's logic design in the structured ASIC. For example, these customizable masks may determine what logic function options are performed by basic logic units in the device, and also what logic unit interconnection options are employed.
Although highly developed techniques may be employed to minimize operational differences between the user's logic design as implemented in a programmed FPGA and as implemented in a structured ASIC, some such differences may occur. These differences may be small or subtle (e.g., in the relative timing of various signals on the two types of devices), but they may have a deleterious impact on the performance of the structured ASIC relative to the programmed FPGA. Once the structured ASIC has been fabricated, however, adjusting its performance may be impossible without changing one or more masks and fabricating the product anew.